GVC736CE101 3BHE039203R0101 5SXE12-0184模塊,中文PDF使用手冊
這些位編程串行端口的中斷級別生成級別0不生成中斷。位3當(dāng)該位為高位時(shí)，中斷被啟用。中斷是此位低時(shí)禁用。位4該位控制矢量源。當(dāng)該位較低時(shí)中斷狀態(tài)/id矢量來自串行芯片。當(dāng)這個位高，中斷狀態(tài)/id向量來自PCC。位7當(dāng)該位為高位時(shí)，產(chǎn)生串行端口中斷在位0-2中編程的電平。該位是電平敏感的當(dāng)中斷啟用和串行端口中斷時(shí)，它處于活動狀態(tài)處于活動狀態(tài)。這些位控制本地RAM奇偶校驗(yàn)。
GVC736CE101 3BHE039203R0101 5SXE12-0184模塊這些位應(yīng)該未在MVME147-010上啟用。這些位通過重置。MVME147上的DRAM奇偶校驗(yàn)處于未定義狀態(tài)通電后的狀態(tài)。讀取未初始化內(nèi)存啟用奇偶校驗(yàn)會導(dǎo)致總線錯誤。全部的應(yīng)寫入DRAM位置以確保正確啟用檢查前奇偶校驗(yàn)。0本地RAM奇偶校驗(yàn)已禁用。1啟用本地RAM奇偶校驗(yàn)，并斷言BERR在當(dāng)前DRAM訪問周期期間（添加1個等待周期）。2本地RAM奇偶校驗(yàn)被禁用。3啟用本地DRAM奇偶校驗(yàn)。BERR被斷言在LANCE、VME的當(dāng)前周期（添加1個等待周期）上，PCC訪問DRAM。BERR在下一個MC68030訪問DRAM的DRAM訪問周期（增加0等待周期）。注意，BERR不僅在下一個MC68030 DRAM訪問周期，但在所有后續(xù)MC68030 DRAM訪問周期。這很有幫助當(dāng)DRAM壞時(shí)，停止MC68030繼續(xù)。該位用于測試奇偶校驗(yàn)生成和檢查邏輯。當(dāng)該位較低時(shí)，將正確的奇偶校驗(yàn)寫入DRAM；當(dāng)奇偶校驗(yàn)為高時(shí)，將不正確的奇偶校驗(yàn)寫入DRAM。這一位是通過重置清除。位3設(shè)置時(shí)，該位用于啟用本地總線計(jì)時(shí)器，即PCC的一部分。因?yàn)閂MEchip還包含一個本地總線定時(shí)器，應(yīng)清除該位，關(guān)閉PCC本地總線計(jì)時(shí)器。該位通過重置清除。位4該位為主中斷啟用。當(dāng)該位較低時(shí)，所有MVME147上的中斷被禁用；高時(shí)，所有中斷已啟用。該位通過重置清除。位5-7當(dāng)模式%101寫入這些位時(shí)，前面板重置開關(guān)被禁用。復(fù)位開關(guān)可用于任何其他模式。這些位通過重置清除。
These bits program the interrupt level that the serial ports
generate. Level 0 does not generate an interrupt.
Bit 3 When this bit is high, the interrupt is enabled. The interrupt is
disabled when this bit is low.
Bit 4 This bit controls the vector source. When this bit is low, the
interrupt status/id vector comes from the serial chip. When this
bit is high, the interrupt status/id vector comes from the PCC.
Bit 7 When this bit is high, a serial port interrupt is being generated
at the level programmed in bits 0-2. This bit is level sensitive
and it is active when interrupt enable and serial port interrupt
are active.These bits control local RAM parity checking. These bits should
not be enabled on the MVME147-010. These bits are cleared by
reset. The DRAM parity on the MVME147 is in an undefined
state after power-up. Reads to uninitialized memory
with parity checking enabled causes bus errors. All
DRAM locations should be written to ensure correct
parity before checking is enabled.
0 Local RAM parity checking is disabled.
1 Local RAM parity checking is enabled and BERR is asserted
during the current DRAM access cycle (adds 1 wait cycle).
2 Local RAM parity checking is disabled.
3 Local DRAM parity checking is enabled. BERR is asserted
on the current cycle (adds 1 wait cycle) for LANCE, VME,
and PCC accesses to DRAM. BERR is asserted on the next
DRAM access cycle for MC68030 accesses to DRAM (adds 0
wait cycles). Note that not only is BERR asserted during the
next MC68030 DRAM access cycle but it is asserted during
all subsequent MC68030 DRAM access cycles. This helps
stop the MC68030 from proceeding when DRAM is bad.This bit is used to test the parity generating and checking logic.
When this bit is low, correct parity is written to the DRAM;
when high, incorrect parity is written to the DRAM. This bit is
cleared by reset.
Bit 3 When set, this bit is used to enable the local bus timer that is
part of the PCC. Because the VMEchip also contains a local bus
timer, this bit should be cleared, turning off the PCC local bus
timer. This bit is cleared by reset.
Bit 4 This bit is the master interrupt enable. When this bit is low, all
interrupts on the MVME147 are disabled; when high, all
interrupts are enabled. This bit is cleared by reset.
